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Design+ Defect-oriented BIST for AMS circuits

Figure 10. Monte Carlo simulations for verification of detection of gate-drain short defect in transistor M1 through VG _INV detector
1
Table 4. Converted codes after performing a “one‑hot” test for bit 12, in the presence of each defect in NMOS and PMOS switch

Bit Fault Defect‑free code (Hex) Converted code with Injected Converted code with Injected
Faults for PMOS switch Faults for NMOS switch
Bit 12 Drain-open 3777 3707 3701
Source-open 3777 3707 3701
Gate-open 3777 3703 3701
Gate-drain short 3777 3603 3603
Gate-source short 3777 0651 0001
Drain-source short 3777 3701 3701
Abbreviations: NMOS: N-channel metal-oxide-semiconductor; PMOS: P-channel metal-oxide-semiconductor.

diagnosis will provide valuable information for future minimizes area overhead and power consumption, making
designs as well as the implementation of functional safety it a highly practical and cost-effective solution. The
measures for the circuit. effectiveness of this approach is demonstrated through the
development of a BIST for a 12-bit SAR ADC. Importantly,
4. Conclusion this BIST methodology achieves full defect coverage without
In this paper, we introduce a novel approach to address the additional BIST circuitry for the subcircuits, except for small
growing need for defect-oriented testing in AMS circuits. digital monitors used in the sampling switch BIST. The
This approach relies on breaking down complex AMS proposed test mode operation can be seamlessly integrated
circuits into smaller, more manageable subcircuits, which into the manufacturing process as a post-manufacturing test
are then thoroughly tested using purely digital monitors or employed in the field, running before circuit start-up or
and/or injectors. An important feature of this methodology at any time on demand. This flexibility enhances its utility
is its resource-efficient design. Before incorporating any across various applications and industries.
injector or monitoring circuits, careful consideration
optimizes the utilization of the circuit’s existing resources. Acknowledgments
This strategic approach ensures that the proposed BIST None.

Volume 1 Issue 1 (2024) 12 doi: 10.36922/dp.4351