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Design+ Defect-oriented BIST for AMS circuits

(2) Conversion for bit j: the bootstrapped capacitor, C , the total defects possible
bs
Now when writing the conversion equation for bit j, the for the defect coverage consideration adds up to 62.
value of V for this step will be:
N With comprehensive nodal analysis of the bootstrapped
2 j C 2 k C 2 j C switch, in the presence and absence of each defect, we can
unit
unit
unit
V ( C Total C Total ) V j C Total V N (IV) identify the crucial nodes as V , V , and V . We can
ref
G1
G8
out
take the gate-drain short defect in transistor M11, as an
The term including V on the left side of Equation IV is example, illustrating the detection of the defect through
ref
positive since j>k. However, the total value of the left-hand monitoring the node V . If we set Vin to be equal to VDD,
out
side of Equation IV depends on the value of V. Although the voltage at V node should also be at the VDD level
out
j
we do not know V, we know that it cannot take a negative while the clock (CLK) is high. When CLK is low, it must
j
value. Hence, considering the worst case—from a defect remain at logic high since M1 is off. However, if a gate-
detection point of view—V will be ‘0’, and V will be drain short defect occurs in M1, the V voltage drops to
out
N
j
positive, leading to a ‘0’ for the comparator’s output and no GND level through M9 and M10 transistors.
reflection of the defect in the code. By employing three digital detectors to monitor the
(3) Conversion for bit i and i<j: crucial voltage nodes V , V and V , all 62 possible
out
G1
G8
defects are detected achieving a 100% detect coverage.
For this step of conversion, the equation for determining These detectors are shown in Figure 6, distinguished from
V is as follows:
N the main circuit by blue color.
k
j
i
2 C 2 C 2 C The monitoring detectors used are simple inverters
+
V ( unit − unit )(V − V ) unit = specifically designed to monitor the respective nodes.
ref C Total C Total ref j C Total The design of the monitors starts with categorizing the
k
2 C defects based on the node that can identify them. Then,
V N (1 − unit ) (V) we recorded the out-of-the-range voltages gathered by
C
Total conducting comprehensive PVT and Monte Carlo (MC)
simulations for each defect in each category. Finally, based
The (1−2 C /C Total ) term on the right-hand side is on the collected data, detectors were designed to identify
k
unit
positive, hence not changing the sign of the left side of their designated defects under and PVT variation.
the equation when dividing the left side by this term. The
second term on the left side of the equation is also positive 3. Results and discussion
since V is always greater than V. However, to determine Comprehensive simulations were performed for each
j
ref
the sign of the first term, we need to consider the value of of the test methods proposed in the previous section to
‘i’ in comparison with ‘k’. ensure the correctness and robustness of the proposed
1. If i>k: The first term only, including V , will be BIST. Simulations were conducted while considering the
ref
negative. In this case, V can be positive or negative fact that the probability of multiple defects occurring
N
depending on V, and the i bit in converted code can simultaneously is very low. Therefore, for each defect
20
j
th
be ‘0’ or ‘1’. simulation, only one defect was induced at a time, and its
2. If i<k: The first term will be positive, resulting in effect was investigated. Defect coverage for this work is
a positive value for V and a ‘0’ at the comparator’s calculated based on the universal defect coverage equation
N
output. Since i<k, the defect-free code for this bit as follows: 4
should be ‘1’, but now we are receiving a ‘0’ for this bit Total weighted numberof
thus detecting the defect.
If we analyze the conversion steps in the presence of Defect coverage = defectsdetected ’ ×100 (VI)
each defect for all the bits, we notice that the defects can be Allddefects in circuitss
detected as an alteration in the expected defect-free code. defectuniverse
2.3.5. BIST for constant VGS bootstrapped switch
The numerator of the defect coverage equation is
The bootstrapped switch shown in Figure 5 is the generally defined as the weighted number of the total
commonly used switch for connecting the Vin line to defect to account for the different probability of the defect
the capacitor array. The switch consists of 10 CMOS occurrences. However, in most cases, the probability
21
transistors. Considering the mentioned six defects defined of occurrence is considered equal for all defects. In this
for CMOS transistors and two short and open defects for work, assuming that defects have the same probability of
Volume 1 Issue 1 (2024) 8 doi: 10.36922/dp.4351