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Design+ Defect-oriented BIST for AMS circuits

(OUT-). If the negative input of the comparator has a conversion phase, and a normal binary search was started
voltage level of +LSB, the difference between positive input from the most significant bit (MSB). Normally, with no
(IN_P) and negative input (IN_N) would be -LSB, causing defect in the circuit, the expected code after conversion
the OUT+ to be at logic low and OUT- to be at logic high must be all zeros from the MSB to and including the kth
level. On the other hand, by having IN_N = -LSB V, the bit and all ones from the (k-1) bit to the LSB. However,
th
difference between the positive input and negative input the occurrence of a defect can change this code enabling us
will be +LSB; hence, OUT+ must be at logic low and, to detect the defect.
respectively, OUT- must be at logic high. By analyzing the conversion equations for the defect-
The output of the comparator takes these logic levels in free and defective cases, we can observe how each defect
the mentioned scenarios, if and only if there are no defects will affect the expected code. In the defect-free case, based
in any of the 17 CMOS transistors. However, if any of the on the charge conservation law, we can write the following
mentioned 102 defects occur – except for the drain-source equation as the total charge stored after the pre-charge
short defect in M7, which will be discussed in section V – stage:
at least one of the two outputs of the comparator changes k
from the expected logic level to the opposite logic level, in Q = V ..2 C unit (I)
T
ref
at least one of the +LSB or -LSB scenarios.
Starting from the above equation and writing the
Bringing the voltage level at IN_N to +LSB is simply
enabled by sampling the VDD voltage, meaning setting equations for each conversion step, the effect of any defect
in the PMOS and NMOS switches of the kth bit and any
the Vin to be equal to VDD. Then, connecting the bottom bit more significant than the kth bit can be identified in the
plate of all the bits in the capacitive array to the VDD line, converted code.
except for the LSB bit, which should be connected to the
ground line in the circuit (GND). This would be equivalent Let us take any open defect of the kth bit’s PMOS switch
to setting the code for the DAC to all ‘1’s, except for the as an example. In this case, the total charge stored in pre-
LSB bit (111.10). charge stage IS zero, and the converted code received after
the test is the defect-reflected code of all zeros. Now, let us
Similarly, to bring the IN_N voltage level to -LSB V,
we only need to sample the GND level, Vin=0, and set the consider any open defect for an NMOS switch at the “j ”
th
bit (j>k) as another example. In this case, the total charge
code in DAC to all ‘0’s, except for the LSB bit, which should stored from the pre-charge stage will be as follows:
be set to high logic (000.1).
The presented test mode operation, which only Q V ..2 k C unit V ..2 j C unit (II)
T
j
ref
utilizes the ADC resources and requires no additional test
circuitry, has been shown to achieve 100% defect coverage. In the above equation, V represents the potential stored
We will discuss the coverage results in depth in the results in the j bit’s capacitor, which is unknown. If we perform
j
th
and discussion session. the normal binary search from the MSB, three situations
2.3.4. BIST for capacitive DAC can be considered:
The BIST for the capacitive DAC was developed by carefully (1) Conversion for bit i and i>j>k:
analyzing charge conservation in the capacitive binary array. By writing the conservation equations and deriving
We introduced the “one-hot” test, which was developed by them to determine the voltage value at the negative input
methodically investigating the effect of each defect on the of the comparator, V , we will have the following equation:
charging phase and conversion phase, the “one-hot” test N
consists of two phases: pre-charge and conversion. This 2 i C 2 k C
test can be performed for any bit and enables full defect V ( unit j unit ) V N (III)
ref
j
detection and diagnosis of the capacitive DAC. C Total 2 C unit C Total 2 C unit
We will explain the introduced “one-hot” test for a C is the summation of the weights of the capacitors
Total
random bit called the kth bit. In the pre-charge phase, all in the capacitive DAC, and 2 C is the weight of the
k
the capacitor arrays are connected to the GND line through unit i
the NMOS switches, except for the kth bit. The kth bit is capacitor at the kth bit. Similarly, 2 C unit is the weight of
connected to the VDD line through the PMOS switch, the capacitor array at the i th bit. Since i>k, the value of VN
referring to the test name “one-hot.” For the conversion derived from Equation III will be positive, and the
stage, the kth bit is connected to the GND line during the comparator’s output will be ‘0’, not reflecting the defect.

Volume 1 Issue 1 (2024) 7 doi: 10.36922/dp.4351