Page 68 - IJOCTA-15-3

M. A. Touat / IJOCTA, Vol.15, No.3, pp.435-448 (2025)
finally implemented on the hardware (FPGA) and
then tested on the Simulink environment through
the FIL functionality. 21 In this study, the Xilinx programmed as 8 bits. The controller output was
Zedboard is used, which has a Zynq-7000 AP SoC
XC7Z020-CLG484-1 FPGA. 35
FIL mode simulation is performed for real-
time DC motor position control. The generated
VHDL code is executed in the target hardware
to control the DC motor model synthesized in
Simulink. The Zedbaord exchanges the send data
of position and signal control in each sampling
period with the Simulink environment via the
JTAG communication protocol. The concept of
FIL simulation is described in Figure 4.
FPGA In-the Loop simulation
Control system FMRLC controller
JTAG
connection
Computer-MATLAB Zedboard Zynq-7000
/Simulink
Figure 4. FPGA in-the loop diagram
4.3. Experimental implementation
4.3.1. Experimental setup
The control system consists of a 12 V DC motor
(model DFRobot 28PA51G) equipped with a Hall
Effect encoder and an adapter board for the en-
coder (FIT0324) Figure 5, which allows to recover
the motor shaft position signal. The encoder can
provide 675 pulses per revolution, with a maxi-
mum speed of 143 rpm. This motor is connected
to an L298N (H-bridge) module, which will allow
to change the speed and direction of the motor
rotation.
The reference signal was generated by an-
other encoder similar to the motor’s. The con-
troller, the two encoders, and the PWMs were
programmed using Simulink blocks supported
440
by HDL Coder. The encoder output was pro-
grammed as 16 bits, while the PWM input was
calculated using the Fixed-Point Tool by combin-
ing 16-bit integers and fractions to ensure accu-
racy. Figure 6 shows the control diagram devel-
oped in the Simulink environment.
This model was implemented via HDL Coder
from Simulink, by ”HDL Workflow Advisor”
through the ”IP Core Generation” functionality.
This technique makes it possible to generate an
IP block (Figure 7), whose target hardware is the
zynq-7000 FPGA. Next, the VHDL code is gen-
erated from the IP block, which is then imple-
mented on the Zedbaord as a bitstream program-
ming file.
The implementation blocks obtained using the
Vivado software are as follows:
The encoder block (Figure 8) has two logic
inputs, A and B, representing the square-wave
signals provided by the sensor, and a 16-bit in-
teger output (int16) representing the position of
the motor shaft (in pulses).
Figure 9 shows the PWM block, which in-
cludes an input u (the control signal) coded on
8 bits (unit8) and an output that is the DC mo-
tor supply voltage.
The FMRLC controller block (Figure 10) has
an input e, which is the error between the de-
sired position and the measured position, coded
in fixed point on 16 bits (fixdt(1, 16, 8)) and an
output u, which is the control signal, also coded
in fixed point on 16 bits (fixdt(1, 16, 6)).
The PID controller block is shown in Figure
11, it has the position error e as an input and
the control signal u as an output, both coded in
fixed point to 16 bits ((fixdt(1, 16, 8)) for e and
(fixdt(1, 16, 4)) for u).
Details of the implementation of the PID and
FMRLC controllers on the Zedboard FPGA are
given in Table 3. These results are obtained in
both cases using the 16-bit fixed-point data type.
The controller execution time depends on the
controller complexity and the number of bits used
for the signals. As can be seen, the PID has a
lower propagation time than the FMRLC due to
the large number of blocks it contains.
Table 3. Features of PID and FMRLC controller
implementation on the Zedboard FPGA
Controller Bits Propagation Maximum
frequency
PID 16 14.14 (ns) 70.85 (MHz)
FMRLC 16 98.115 (ns) 10.19 (MHz)
4.3.2. FPGA resources
Despite the complexity of the algorithm, the use
of the fixed-point tool allows to obtain an optimal