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Design+ Approximate signed multipliers design approach

As technology advances to sub-20 nm scales, power The remainder of the paper is organized as follows:
consumption has become a serious challenge. 12-15 Section 2 presents the prerequisites of the paper, including
Approximate computing has emerged as an interesting the Baugh–Wooley multiplication algorithm and a brief
paradigm in the realm of DIP and AI due to its potential review of previous works. Section 3 details the proposed
to significantly enhance computational efficiency and approach. In Section 4, we provide simulation results,
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reduce energy consumption. The tasks in these fields including hardware performances, accuracy analyses,
often involve large-scale data processing that can and the implementation of the proposed methods in NN
tolerate minor inaccuracies without compromising applications. Finally, Section 5 concludes the paper.
overall functionality. 17-20 Approximate multipliers, a key
component in this approach, are specifically designed to 2. Study background
trade off a small degree of accuracy for substantial gains in 2.1. Signed multiplication
speed, power consumption, and area. 18,21,22 This makes them
particularly valuable in DIP applications where real-time The Baugh–Wooley algorithm is a commonly used method
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processing is crucial and in AI algorithms that can benefit for performing signed multiplication. This algorithm
from faster and more energy-efficient computations. 23-25 leverages both AND and NAND gates to generate partial
products (PPs) and is structured into three main steps to
Approximate signed multipliers enhance hardware correctly handle the signed nature of the operands and
efficiency, reduce power consumption, and improve produce accurate results:
performance. However, since signed numbers are (i) Complementing the most significant bits (MSBs): The
1
typically encoded using one’s or two’s complement first step involves complementing the MSBs of each
system, conventional methods of designing approximate row of PPs. In addition, all bits of the last row of PPs
multipliers often lead to a significant accuracy loss in are complemented, except for the MSB of that last row.
approximate signed multipliers. As digital systems This step is crucial for handling the sign bits correctly,
1,21
evolve, the use of signed systems becomes increasingly ensuring that the PPs are aligned properly according
critical as building blocks for high-performance and error- to the rules of signed binary multiplication
tolerant computations. Considering these facts, developing (ii) Adding a “1” to the MSB and performing addition: In
high-accuracy and efficient methods for designing the second step, a “1” is added to the MSB of the first
approximate signed multipliers is crucial. 1,26 row of PPs to correctly represent the signed numbers
In this paper, we propose a novel approach for during the intermediate stages of multiplication.
designing approximate signed multipliers. Unlike previous After this adjustment, the PPs are summed together,
approximate multiplier designs, the proposed approach accounting for the two’s complement representation
eliminates the need for signed-to-unsigned converters, used for signed numbers
resulting in reduced area overhead and lower power (iii) Complementing the MSB of the final result: The final
consumption while maintaining acceptable accuracy. In step involves complementing the MSB of the resultant
addition, the proposed approach is flexible and not limited sum from the previous step. This adjustment ensures
to any specific compressor, allowing the use of various that the final product maintains the correct sign
compressors in the multiplier design. The approximate according to the rules of signed arithmetic.
multiplier designed using this approach can be used in a Figure 1 illustrates an example of 8-bit signed
wide range of applications, including DIP, NNs, and AI multiplication using the Baugh–Wooley algorithm.
hardware accelerators. The Baugh–Wooley algorithm effectively manages the
The main contributions of this paper are as follows: complexities of signed multiplication by systematically
• Introduction of a new method for designing handling the sign bits and ensuring accurate generation
approximate signed multipliers without converting and addition of PPs.
signed numbers to unsigned ones
• Detailed comparison of power usage, delay, power- 2.2. Previous works
delay product (PDP), and transistor count The design of signed approximate multipliers involves a
• Validation of the functionality and performance of more careful balance between computation accuracy and
the proposed method using basic and three advanced energy efficiency compared to unsigned approximate
compressors from other studies multipliers. Various architectures achieve this balance by
• Proposal of a new figure of merit (FoM) for evaluating employing different techniques to introduce controlled
the accuracy and performance of approximate approximations. Here, we review three prominent signed
multipliers in different applications. approximate multiplier architectures:

Volume 1 Issue 1 (2024) 2 doi: 10.36922/dp.3882