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Design+ Approximate signed multipliers design approach

The proposed approach uses exact compressors along the
sign bit path to ensure it remains unchanged, forming the
foundation of the approximate signed multiplier design.
Figure 2 illustrates the proposed 8-bit approximate signed
multiplier using this method. In this design, the sign bit of
the final product is derived using an XOR gate on the input
sign bits, and a three-input XOR gate is used to generate
the (n-1) bit of the output, preventing carry overflow.
The design shown in Figure 2 ensures the stability
of the sign bit and prevents overflow errors through the
strategic use of a three-input XOR gate. By representing
negative numbers in two’s complement, where negative
Figure 1. 8-bit signed multiplication using the Baugh–Wooley numbers have a MSB of one, and using exact compressors
algorithm 27 in higher-value columns, the design minimizes errors
when multiplying negative numbers. Furthermore, since
(i) Truncated signed multipliers: Truncated multipliers NN weights typically follow a normal distribution, leading
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might be applicable to signed numbers, but they to a higher likelihood of MSBs being “0” rather than “1,”
require careful consideration. For two’s complement approximate compressors are utilized in the lower part
signed numbers, truncating lower-order bits can lead of the PPs to optimize performance without significant
to significant accuracy loss and may impact the sign accuracy loss.
bit, potentially introducing high errors in the signed
multiplication results. 3.2. Optimization of the proposed approach for
(ii) Approximate booth-signed multipliers: Approximate highest efficiency
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booth multipliers can be adapted for signed numbers The proposed method aims to boost hardware efficiency
with specific modifications. The booth encoding while maintaining sufficient accuracy. It strategically uses
technique inherently handles signed numbers by approximate compressors in positions corresponding to
encoding positive and negative values differently. NN weights, which typically follow a normal distribution,
However, introducing controlled approximations especially in bits likely to be “0.” In signed multipliers, the
requires special handling to ensure accurate sign MSBs are initially complemented and assigned to precise
propagation. compressors, with approximate compressors applied to the
(iii) Probabilistic signed multipliers: Probabilistic less significant bits, as shown in Figure 2. This arrangement
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multipliers can be used with signed numbers, but achieves better hardware efficiency with minimal accuracy
their applicability depends on the nature of the signed compromise, as depicted in Figure 3, where some exact
number representation and the specific probabilistic compressors are replaced with approximate ones.
approach used.
In the optimized multiplier design shown in Figure 3,
Designing approximate signed multipliers requires
careful management of sign propagation and error control the strategic use of approximate compressors reduces
hardware usage, lowers power consumption, and simplifies
to maintain result integrity. Typically, these designs computations. Crucially, this design adheres to the two core
increase hardware requirements, leading to higher power design principles discussed earlier, ensuring that errors in
consumption and performance degradation.
signed number multiplication remain within acceptable
3. Proposed approach limits. In addition, the proposed design eliminates the
need for extra circuits to convert between signed and
This section introduces the proposed approach for hardware unsigned numbers. Although this design is more complex
implementation of approximate signed multipliers. First, than an unsigned multiplier, it ultimately reduces the total
we present the main idea behind the proposed approach, area needed for implementing a signed multiplier.
followed by the design of an 8-bit approximate signed
multiplier architecture. Finally, the proposed approach is 4. Results and discussion
optimized to achieve the highest hardware efficiency.
4.1. Circuit-level evaluation
3.1. Main idea The proposed multiplier, alongside other state-of-the-art
In signed multiplier designs, preserving the sign bit is crucial approximate and exact multipliers detailed in Arasteh
to avoid significant errors, unlike in unsigned multipliers. et al., was simulated utilizing HSPICE with a 7 nm FinFET
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Volume 1 Issue 1 (2024) 3 doi: 10.36922/dp.3882