Page 63 - DP-1-1

Design+ Approximate signed multipliers design approach

latch. IEEE Magn Lett. 2020;11:1-5. 23. Waris H, Wang C, Liu W, Han J, Lombardi F. Hybrid partial
product-based high-performance approximate recursive
doi: 10.1109/lmag.2020.3036834
multipliers. IEEE Trans Emerg Top Comput. 2022;10(1):
13. BahmanAbadi M, Amirany A, Jafari K, Moaiyeri MH. 507-513.
Efficient and highly reliable spintronic non-volatile doi: 10.1109/tetc.2020.3013977
quaternary memory based on carbon nanotube FETs
and multi-TMR MTJs. ECS J Solid State Sci Technol. 24. Yin P, Wang C, Waris H, Liu W, Han Y, Lombardi F. Design
2022;11:061007. and analysis of energy-efficient dynamic range approximate
logarithmic multipliers for machine learning. IEEE Trans
doi: 10.1149/2162-8777/ac77bb Sustain Comput 2021;6(4):612-625.
14. Mehri S, Amirany A, Moaiyeri MH, Jafari K. Theoretical doi: 10.1109/tsusc.2020.3004980
circuit design of an efficient spintronic random number
generator with an internal post-processing unit. IEEE Magn 25. Almurib HAF, Kumar TN, Lombardi F. Approximate DCT
Lett. 2022;13:1-5. image compression using inexact computing. IEEE Trans
Comput. 2018;67(2):149-159.
doi: 10.1109/lmag.2022.3200326
doi: 10.1109/tc.2017.2731770
15. Amirany A, Moaiyeri MH, Jafari K. MTMR-SNQM:
Multi-Tunnel Magnetoresistance Spintronic Non- 26. Ejtahed SAH, Timarchi S. Efficient approximate multiplier
volatile Quaternary Memory. In: Presented at: 2021 IEEE based on a new 1-gate approximate compressor. Circuits Syst
st
51 International Symposium on Multiple-Valued Logic Sig Process. 2022;41(5):2699-2718.
(ISMVL); 2021. doi: 10.1007/s00034-021-01902-7
16. Amirany A, Meghdadi M, Moaiyeri MH, Jafari K. Stochastic 27. Baugh CR, Wooley BA. A two’s complement parallel array
Spintronic Neuron with Application to Image Binarization. multiplication algorithm. IEEE Trans Comput. 1973;C-
In: Presented at: 2021 26 International Computer Conference, 22(12):1045-1047.
th
Computer Society of Iran (CSICC); 2021.
doi: 10.1109/t-c.1973.223648
17. Amirany A, Rajaei R. Nonvolatile, spin-based, and low-
power inexact full adder circuits for computing-in-memory 28. Osorio RR, Rodriguez G. Truncated SIMD multiplier
architecture for approximate computing in low-power
image processing. Spin. 2019;9(3):1950013. programmable processors. IEEE Access. 2019;7:56353-
doi: 10.1142/s2010324719500139 56366.
18. Sayadi L, Timarchi S, Sheikh-Akbari A. Two efficient doi: 10.1109/access.2019.2913743
approximate unsigned multipliers by developing new 29. Waris H, Wang C, Liu W. Hybrid low radix encoding-based
configuration for approximate 4:2 compressors. IEEE Trans approximate booth multipliers. IEEE Trans Circuits Syst II
Circuits Syst I Regular Pap. 2023;70(4):1649-1659. Exp Briefs. 2020;67(12):3367-3371.
doi: 10.1109/tcsi.2023.3242558 doi: 10.1109/tcsii.2020.2975094
19. Avan A, Taheri M, Moaiyeri MH, Navi K. Energy-Efficient 30. Sang-Min K, Jin-Gyun C, Parhi KK. Low error fixed-
approximate compressor design for error-resilient digital width CSD multiplier with efficient sign extension. IEEE
signal processing. Int J Electron. 2022;110(9):1-23. Trans Circuits Syst II Analog Digit Sig Process. 2003;50(12):
doi: 10.1080/00207217.2022.2117854 984-993.
20. Rajaei R, Amirany A. Nonvolatile low-cost approximate doi: 10.1109/tcsii.2003.820231
spintronic full adders for computing in memory 31. Arasteh A, Hossein Moaiyeri M, Taheri M, Navi K,
architectures. IEEE Trans Magn. 2020;56(4):1-8. Bagherzadeh N. An energy and area efficient 4:2 compressor
doi: 10.1109/tmag.2020.2974142 based on FinFETs. Integration. 2018;60:224-231.
21. Spagnolo F, Corsonello P, Frustaci F, Perri S. Efficient doi: 10.1016/j.vlsi.2017.09.010
implementation of signed multipliers on FPGAs. Comput 32. Clark LT, Vashishtha V, Shifren L, et al. ASAP7: A 7-nm
Electr Eng. 2024;116:109217. finFET predictive process design kit. Microelectronics J.
doi: 10.1016/j.compeleceng.2024.109217 2016;53:105-115.
22. Strollo AGM, Napoli E, De Caro D, Petra N, Saggese G, Di doi: 10.1016/j.mejo.2016.04.006
Meo G. Approximate multipliers using static segmentation: 33. Ha M, Lee S. Multipliers with approximate 4–2 compressors
Error analysis and improvements. IEEE Trans Circuits Syst I and error recovery modules. IEEE Embedded Syst Lett.
Regular Pap. 2022;69(6):2449-2462. 2018;10(1):6-9.
doi: 10.1109/tcsi.2022.3152921 doi: 10.1109/les.2017.2746084

Volume 1 Issue 1 (2024) 8 doi: 10.36922/dp.3882