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Design+ Approximate signed multipliers design approach

the proposed approach yields competitive results, with 2021;70(3):384-392.
commendable PSNR and SSIM metrics in image sharpening doi: 10.1109/tc.2020.2988404
tasks, and robust classification accuracy in image classification
tasks compared to existing approximate multipliers, further 2. Cherkauer BS, Friedman EG. A hybrid radix-4/madix-8 low
power signed multiplier architecture. IEEE Trans Circuits
validating its effectiveness. Future research directions could Syst II Analog Digit Sig Process. 1997;44(8):656-659.
include optimizing approximate compressors, developing
adaptive approximation techniques, conducting extensive doi: 10.1109/82.618039
application-specific evaluations, integrating the proposed 3. Amirany A, Epperson G, Patooghy A, Rajaei R. Accuracy
design with emerging technologies, and enhancing error adaptive spintronic adder for image processing applications.
management strategies. IEEE Transactions on Magnetics. United States: IEEE; 2021.
p. 1-1.
Acknowledgments doi: 10.1109/tmag.2021.3069161

None. 4. Rezaei M, Amirany A, Moaiyeri MH, Jafari K. A high-
accuracy and low-power emerging technology-based
Funding associative memory. IEEE Trans Nanotechnol. 2024;23:1-6.
None. doi: 10.1109/tnano.2024.3380368
Conflict of interest 5. Rezaei M, Amirany A, Moaiyaeri MH, Jafari K. A Reliable
non-volatile in-memory computing associative memory
Abdolah Amirany is an Editorial Board Member of this based on spintronic neurons and synapses. Engineering
journal but was not involved, directly or indirectly, in the Reports; 2024.
editorial or peer-review process for this paper. Separately, doi: 10.1002/eng2.12902
the other authors declared no known competing financial
interests or personal relationships that could have 6. Iranfar P, Amirany A, Moaiyeri MH, Jafari K. On the
influenced the work reported in this paper. Layout-Oriented Investigation of Power Attack Hardness
of Spintronic-Based Logic Circuits. Circuits Syst Sig Process.
Author contributions 2024;43:3212-3237.
Conceptualization: Faraz Baraati, Abdolah Amirany, Milad doi: 10.1007/s00034-024-02603-7
Tanavardi Nasab 7. Amirany A, Jafari K, Moaiyeri MH. A Task-schedulable
Formal analysis: Abdolah Amirany, Milad Tanavardi Nasab nonvolatile spintronic field-programmable gate array. IEEE
Investigation: Faraz Baraati, Milad Tanavardi Nasab Magn Lett. 2021;12:1-4.
Methodology: Faraz Baraati, Abdolah Amirany, Milad doi: 10.1109/lmag.2021.3092995
Tanavardi Nasab 8. Amirany A, Jafari K, Moaiyeri MH. High-Performance and
Writing – original draft: Abdolah Amirany, Kian Jafari, Soft Error Immune Spintronic Retention Latch for Highly
Reza Ghaderi Reliable Processors. In: Presented at: Electrical Engineering
Writing – review & editing: Abdolah Amirany, Reza (ICEE), Iranian Conference on; 2020.
Ghaderi
9. Lian Y, Yu YJ. Guest editorial: Low-power digital filter
Ethics approval and consent to participate design techniques and their applications. Circuits Syst Sig
Process. 2010;29(1):1-5.
Not applicable. doi: 10.1007/s00034-009-9110-y

Consent for publication 10. Amirany A, Jafari K, Moaiyeri MH. DDR-MRAM: Double
data rate magnetic RAM for efficient artificial intelligence
Not applicable. and cache applications. IEEE Trans Magn. 2022;58:1-1.

Availability of data doi: 10.1109/tmag.2022.3162030
Data used in this work are available from the corresponding 11. Bakhtiary V, Amirany A, Moaiyeri MH, Jafari K. An SEU-
author on reasonable request. hardened ternary SRAM design based on efficient ternary
C-elements using CNTFET technology. Microelectronics
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Volume 1 Issue 1 (2024) 7 doi: 10.36922/dp.3882